Data is often stored as “words” of data in which each word generally comprises a fixed number of bits. Each bit is typically stored in a memory cell. A word of data may be accessed from a memory by activating a particular word line and reading the bits of the accessed word on individual bit lines electrically coupled to cells of the memory. To facilitate accessing a word, the cells of a memory are typically arranged in orthogonal columns and rows.
FIG. 1 shows one example of a prior art array 10 of memory cells 12 arranged in a plurality of columns 14a, 14b . . . 14n and rows 16a, 16b . . . 16n. Each memory cell 12 stores one bit of data. In this example, a word has n bits which are read out on bit lines BL0, BL1 . . . BLn. Each Word WL0 WL1 . . . selects which word to read. Each bit line BL0, BL1 . . . BLn is electrically coupled to each of the cells 12 in a particular row 16a, 16b . . . 16n of the array 10. The bits stored in a particular column 14a, 14b . . . 14n of bit cells 12 may be read by activating a particular word line WL0, WL1 . . . WLn which is electrically coupled to each bit cell 12 of an associated column 14a, 14b . . . 14n of bit cells 12.
There are various types of memory for storing data including read only memory (ROM) and random access memory (RAM). In general, the data stored in a ROM is nonvolatile, that is, it is not lost when power is removed. In addition, data stored in a ROM is frequently unchangeable. However, in some ROM types, data is changeable by a special operation. For example, in flash ROM memory, data may be erased in a section referred to as a block by applying an electric field to each cell of the block. Absent this special operation, data is normally maintained even when power is removed. In contrast, data stored in a RAM is often volatile, that is, it is lost when power to the memory is removed. In addition, data stored in a RAM is frequently readily changeable without utilizing special operations to change the data.
The internal structure of a memory cell may vary depending upon the type of memory. For example, known ROM memory cells may contain a device such as a diode, a programmable fuse, or a field effect transistor (FET). FIG. 2 shows an example of a 4 by 4 array 20 of memory cells 12a and 12b in which each cell 12a is programmed with a logical 1 by placing an FET 22 in each cell 12a as shown. Each cell 12b is programmed with a logical 0 by omitting the placement of an FET in the cell 12b. By placing a signal on a word line such as word line WL0, for example, a signal (representing a logical 1) is propagated by those cells of the column 14a containing an FET 22, that is, cells 12a. Those cells of the column 14a lacking an FET 22, that is, cells 12b, do not propagate the signal representing a logical 1. Hence, signals each representing a logical 1 are propagated on bit lines BL0, BL2 and BL3 because the associated cells 12a of column 14a each contain an FET 22. Conversely, a signal representing a logical 0 remains on bit line BL1 because the associated cell 12b of column 14a does not contain an FET 22 as shown in FIG. 2.
FIG. 3 shows one example of the layout of a portion of a column of bit cells in which two adjacent bit cells 12a each contain an FET 22. Each FET 22 has a source region 30 electrically coupled by a connection region 32 and connection metalizations 34 to a conductive supply line 36 which may be a polysilicon line, for example. The supply voltage may be designated Vss. Each FET 22 further has a drain region 40 electrically coupled by a bit line connection region 42 to an associated bit line such as the bit line BL0, BL1 as shown in FIG. 3.
A conductive line 50 is connected to each gate of FET's 22 of the column of memory cells 12a, 12b. The conductive line 50 may be formed of polysilicon, for example, and provides a word line such as word line WL3 [FIG. 2], for example. A signal applied to conductive line 50 is propagated to the bit lines BL0, BL1 as a logical 1 signal on each bit line BL0, BL1.
FIG. 4 shows an example of a prior art memory circuit 60 which includes ROM array with 14-banks Bank0, Bank1 . . . Bank13 in this example. The circuit 60 is divided into two sections, a high section 60a and a low section 60b each of them containing 14 banks each [Bank0, Bank1 . . . Bank13]. Within each bank Bank0, for example, words/bits are arranged to form an array of ROM cells. Associated with each section 60a, 60b is input/output (I/O) circuitry 62a, 62b which includes keeper circuitry for maintaining voltage levels, precharge circuitry and clock distribution circuitry.
As previously mentioned a word line or a portion of a word line such as the word line 50 may be formed of polysilicon material. In order to reduce word line resistance, a “strapping” cell may be used to strap the polysilicon word line with a strapping line formed of an upper-layer low resistance conductive metal material. FIG. 5 shows a portion of a column 70 of ROM cells 12 having a common polysilicon word line 50. As shown in FIG. 5, interspersed with the ROM cells 12 is a strapping cell 72 to strap the polysilicon word line 50 with a strapping line 74 formed by an upper-layer conductive metal material. In this example, a strapping cell 72 is positioned in the column 70 every twelve cells of the ROM memory cell 12 type.